Wide & Slow = Low Power & Latency
24G per lane, <<1 pJ/bit, sub-5ns latency
10000s of lanes = >200 TB/s of bandwidth
No external lasers
Integrated micro-VCSEL arrays
Integrated Waveguides
>2500X smaller than optical fiber
Electrical wires on an interposer travel about 2 millimeters. Our optical waveguides on an interposer travel 200mm+, breaking the shoreline limit of HBM-based systems, letting us aggregate 100x chiplets into a single, ultra-high-bandwidth memory pool.
Reach breaks the memory wall
The electrical reach limit
Electrical wires travel ~2–5mm, less than the ~11mm length of an HBM stack. This limits existing chips to a small amount of memory and bandwidth.
Our optical wires travel 200mm+
Breaking the shoreline limit that caps HBM capacity and bandwidth, over 220 memory chiplets can be connected in a single, uniform-latency memory pool. This enables gigantic capacities while simultaneously running at ultra-high bandwidth.
We break the tradeoff between memory bandwidth and memory capacity.
Enabling multi-trillion parameter models at low latencies.
We run >10T models at SRAM-system speeds
For the first time
The high bandwidth of SRAM has enabled low latency inference, critical for the agentic era. But the size limits of SRAM prevent running large models with large contexts.
We enable both, for the first time.
No external lasers, thermally stable at >95C, <<1 pJ/bit
Clear open Eye
BER <1e-12 at wafer-scale with over >10x electrical reach
World's 1st optical interposer with no external lasers (fully integrated)
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